FREMONT, CALIF. -- Yield Engineering Systems (YES), a leading provider of process equipment for advanced packaging for AI and HPC systems, announced that it has received multiple orders of VeroTherm™ and VeroFlex™ reflow systems from one of the largest memory suppliers. These systems will enable 3D stacking of memory and logic chips for high-performance AI accelerators, driven by large language model (LLM) applications.

The VeroTherm™ and VeroFlex™ reflow systems are designed to provide solutions for achieving sub-10μm micro-bump structures with fluxless solder and mass reflow processes in a low vacuum environment for wafers and panels respectively. These systems enable superior quality and total cost of ownership (CoO), particularly for the manufacturing of advanced packaging architectures such as stacked logic and high bandwidth memory (HBM) that are an integral part of AI accelerators.

“The VeroTherm™ and VeroFlex™ process platforms deliver enhanced thermal uniformity and mechanical reliability for advanced packaging applications requiring ultra-fine pitch interconnects. Our validation studies demonstrate zero-defect reflow performance with no evidence of bump fracture or structural collapse at pitches as aggressive as 10μm,” said Rezwan Lateef, President of YES. “The proprietary process architecture achieves deterministic solder joint formation while maintaining statistical process control metrics that enable high-volume manufacturing with optimized cost-per-unit economics. These customer adoptions represent significant technical validation of our solution in the heterogeneous integration and 3D-IC assembly market segments,” Lateef added.

According to Alex Chow, SVP of Sales and Business Development and Asia President at YES, “Our VeroTherm™ and VeroFlex™ product families offer vacuum processing with unique capabilities of removing oxides and reflowing solder into excellent bump shapes without defects found in older atmospheric pressure systems. These tools eliminate SnAg agglomerate defects and rough surfaces while minimizing inter-metallic compound zones, extending down to sub-10μm pitches.”